Method for fabricating stacked capacitors with increased capacitance in a DRAM cell

摘要

A method is described for fabricating a dynamic random access memory having a high capacitance stacked capacitor. Gate structures and associated source/drain structures are formed within the device areas. A first silicon oxide layer is formed over the device and field oxide areas. The stacked capacitors are now formed by first depositing a thick second polysilicon layer over the device and field oxide areas. Openings are formed to the desired source/drain structures by etching through the second oxide, second polysilicon, and first oxide layers. Cavities are formed between the first and second oxide layers by laterally etching the second polysilicon layer. A third polysilicon layer is deposited over the device and field oxide areas. The second and third polysilicon layers and the first and second oxide layers are patterned so as to have their remaining portions over the planned capacitor areas. The layers are etched leaving the third polysilicon layer as the bottom storage node electrode contacting the source/drain structures. The remaining second and third polysilicon layers form the storage node of the capacitor. A capacitor dielectric layer is formed over the bottom electrode polysilicon layer. A contact polysilicon layer is deposited as the top plate electrode and the contact polysilicon layer and the dielectric layer are patterned to complete the stacked capacitor.