Method for generating test access procedures

摘要

A method is presented for generating test access procedures for digital circuits embedded within larger circuits. The method of the present invention utilizes logical implication techniques to restrict the set of initial possible signal combinations at the inputs of the circuit. The implications allow values to be calculated from input assignments already made. The implication step also allows the exclusion of other values as a result of other assignments already made. In addition, the method of the present invention includes the performance of a netlist transformation technique to model sequential circuits with iterative arrays for purposes of developing proper input signals and calculating expected output values in accordance with standard test synchronizing procedures.