Method to improve interlevel dielectric planarization

摘要

A method is provided for forming a substantially planarized surface of an integrated circuit, and an integrated circuit formed according to the same. A conductive area is formed over a portion of a dielectric region. A first spin-on-glass layer is formed over the conductive area and exposed dielectric region. A second spin-on-glass layer is formed over the first spin-on-glass layer; wherein the second spin-on-glass layer has a slower etch rate than the first spin-on-glass layer. A partial etchback of the first and second spin-on-glass layers is performed forming a substantially planar surface.