| 摘要 |
PURPOSE:To reduce the malfunction of a circuit due to the variation of the wiring delay of a clock by decreasing the number of the latch of a shift register which is operated by the same clock. CONSTITUTION:An angle modulated wave is converted into phase data by a phase quantizing circuit 10, the number of bits of the phase data is compressed by a differentiation circuit 11, and differentiated phase data are outputted. The output of a first integrating circuit 13a which directly expands the differentiated phase data and the output of a second integrating circuit 13b which expands the differentiated phase data passing from a shift register 12 are inputted to a detector 14, a transmitting timing is detected by a detector 14 by an eye pattern obtained by subtracting the two outputs, and outputted to a DPLL (digital phase synchronizing loop) 15. The DPLL 15 operates clock reproduction synchronizing with the signal. |
