| 摘要 |
PURPOSE:To reduce the current consumption for clamping without extending the set-up time of a pair of data busses. CONSTITUTION:When a clamp signal phic goes to the high level, NMOSs 21, 22, 23, and 24 in a clamping circuit 20 are turned on, and clamping of a pair of data busses DB and DB/ to a certain intermediate potential VR2 is started. Just after this start, a driving signal phis rises to the high level, and data busses DB and DB/ are boosted to the intermediate potential VR2 by boosting capacities 25 and 26. Next transfer gates 1a and 1b are turned on by a column line CL, and a pair of bit lines BL and BL/ on which information is put are connected to the pair of data busses D and DB/, and information on bit lines BL and BL/ is transferred to data busses DB and DB/. |
