| 摘要 |
<p>PURPOSE:To enable pipeline processing in a clock cycle shorter than processing time on the stage of long processing time in the integrated circuit for performing the pipeline processing composed of plural stages. CONSTITUTION:This integrated circuit latches data with a first latch 103, inputs the output to a first logic element 106, processes it, latches an output from the first logic element 106 with a second latch 104, inputs an output from the second latch 104 to a second logic element 107 and processes it. When the processing time of the first logic element 106 is longer than that of the second logic element 107, a clock signal to be inputted to the latch 104 on the side of the logic element 107 with the shorter processing time is delayed by a delay element 109, and the delay time is set shorter than the minimum delay time of the logic element 106 with longer processing time. Therefore, the cycle of a pipeline for each stage van be varied, and data processing time can be shortened.</p> |
