发明名称 |
Memory cell array divided type semiconductor memory device |
摘要 |
The memory device of this invention includes a plurality of memory cell blocks each having a plurality of memory cells disposed in a matrix form. A memory cell selector selects a predetermined number of the memory cells in each memory cell block in accordance with external address signals. A sense amplifier unit amplifies data read from the selected memory cells for data read. A data output unit outputs the data amplified by the sense amplifier unit. A block selector selects a desired one or more of the memory cell blocks as data write blocks for data write. A data write unit writes data in the selected memory cells in the selected blocks. A sense amplifier controller supplies, during the data write, a signal to the sense amplifier unit to make the sense amplifier unit inactive, and during the data read supplies a signal to the sense amplifier unit to make the sense amplifier unit active.
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申请公布号 |
US5329494(A) |
申请公布日期 |
1994.07.12 |
申请号 |
US19920848152 |
申请日期 |
1992.03.09 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
SUZUKI, YOUICHI;NAKAMURA, TAKENORI |
分类号 |
G11C11/41;G11C7/06;G11C7/22;G11C11/401;G11C11/409;(IPC1-7):G11C8/00;G11C7/00 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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