| 摘要 |
An architecture and method for performing the known windowing and presumming operations associated with enhancing the performance of a fast Fourier transform (FFT) processor is disclosed. The method makes use of a reordering process in order to enable the multiplying and accumulating processes associated with the windowing and presumming operations to be performed on consecutive data points. In order to apply the appropriate coefficients to the multiplier, coefficients are loaded into a series of registers in a loop configuration in which the coefficient in one register is transferred to an adjacent register upon every clock cycle and the last coefficient register transfers its coefficient to the first register. An accumulator accumulates output from the multiplier and applies it to a delay register. The procedure of accumulating consecutive data points enables a delay register to be used in place of the prior art delay memories, thus enabling specialized chips to be effectively implemented without any random access memory (RAM). Consequently, efficient utilization of specialized integrated chips and memories is attainable.
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