发明名称 CONTROL METHOD OF COMPUTER DEVICE, APPARATUS FOR CONSTITUTION OF DEVICE CONTROL, ARITHMETIC AND LOGIC UNIT AND BINARY COUNTER
摘要 PURPOSE: To automatically optimize a processor control circuit for generating an output sequence of algorithmic generatable values. CONSTITUTION: An ALU 54 is loaded with an initial value and the ALU output is saved in an ALU register 58; and 15 is added to the saved ALU value and the ALU output is saved in an ALU register 59. Then, 14 is subtracted from the saved ALU value and the output is saved in the ALU register, 1 is subtracted and the output is saved in the ALU register, and 15 is added and the output is saved in the ALU register; and 18 is added and the output is saved in the ALU register, 33 is subtracted and the output is saved in the ALU register, and 15 is added and the output is saved in the ALU register. Further, 33 is added and the output is saved in the ALU register, 31 is subtracted and the output is saved in the ALU register, and 31 is added to the saved ALU value and the output is saved in an ALU register 68. An advance to a program step 2 is made and a program loop 2-11 is repeated.
申请公布号 JPH06187131(A) 申请公布日期 1994.07.08
申请号 JP19930208084 申请日期 1993.08.23
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 DEIITAA AANSUTO SUTAIJIYAA
分类号 G01R31/28;G01R31/3181;G06F7/00;G06F7/50;G06F7/506;G06F15/16;G11C29/56 主分类号 G01R31/28
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