发明名称 N-BIT PARITY NEURAL NETWORK ENCODING DEVICE
摘要 PURPOSE:To greatly decrease the number of neuron cells which constitute a hidden layer. CONSTITUTION:A three-layered artificial neural network 50 which has N input terminals, the hidden layer of 1st and 2nd neuron cells 54 and 56, and an output layer of a single neuron cell 52 generates an output parity signal indicating whether or not the number of bits displayed at the N-bit input terminals is even or odd. The bits of the neuron cells 54 and 56 of the hidden layer have an active function for deriving a derivative as to linear response characteristics which can separate the mean weighted sum of input bits into an odd and an even group.
申请公布号 JPH06187319(A) 申请公布日期 1994.07.08
申请号 JP19930173864 申请日期 1993.07.14
申请人 RICOH CO LTD 发明人 DEBITSUDO JII SUTOOKU;JIEIMUSU DEI AREN
分类号 G06F15/18;G06F11/10;G06N3/04;G06N99/00;H03M7/00;H03M13/09;(IPC1-7):G06F15/18 主分类号 G06F15/18
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