发明名称 |
CIRCUITO DI GENERAZIONE DI UN CLOCK DI SCANSIONE IN UN DISPOSITIVO DI ANALISI OPERATIVA DI TIPO SERIALE PER CIRCUITO INTEGRATO |
摘要 |
The circuit comprises first switching means (11) which receive at input a system clock (XTALIN) normally provided for the operation of the integrated circuit and produce at output a machine clock (CK) normally coincident with the system clock (XTALIN), means for clamping (13) the first switching means (11) which after a firing signal of the serial analysis (ENSH) determine the clamping of the state of the machine clock (CK) and second switching means (14) which receive at input the system clock (XTALIN) and are fired by the firing signal (ENSH) to produce a scanning clock (SCK) which repeats the system clock (XTALIN) in an inverted or non-inverted manner according to the state in which the machine clock (CK) has been clamped. <IMAGE> |
申请公布号 |
IT1244205(B) |
申请公布日期 |
1994.07.08 |
申请号 |
IT19900022437 |
申请日期 |
1990.12.19 |
申请人 |
SGS THOMSON MICROELECTRONICS S.R.L. |
发明人 |
SCARRA' FLAVIO;GAIBOTTI MAURIZIO;TRUPIA GIAMPIERO |
分类号 |
G01R31/3183;G01R31/317;G01R31/3185;H03K5/135;(IPC1-7):H03K |
主分类号 |
G01R31/3183 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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