| 摘要 |
PURPOSE: To keep the PLL loop gain almost at a fixed level based on the data transition density of an input data signal. CONSTITUTION: A phase detector 14 forms a feedback loop 12 which includes a charge pump 16 of a loop gain modulator, a loop filter 18 and a VCO 20. A data transition comparator 22 compares the transition of an input data signal VS with that of an output clock VO of the VCO 20 and produces a pulse width modulation control pulse VT. The pulse VT controls the level of a pulse amplitude modulation current pulse IC that is supplied to the filter 18 via the pump 16. At this point, the pulse IC is supplied to the filter 18 in a unique system using both pump 16 and comparator 22. The pulse amplitude is related to the transition density of the signal VS, and the transition density varies as a time function. Accordingly, a PLL dynamically controls the current pulse amplitude. As a result, the loop gain compensates the density variance and is kept at a fixed level. |
