发明名称 MULTIPROCESSOR SYSTEM AND INTER-PROCESSOR COMMUNICATION METHOD
摘要 PURPOSE:To provide a multiprocessor system wherein data can be transferred between processors at a high speed. CONSTITUTION:A multiprocessor system consists of the processors 1 and ATM switches 2 whose number corresponds to the bit width of the internal bus of each processor, each processor 1 has an interface 10 for connecting with the ATM switches 2. Each interface 10 divides a sent data block into plural bit data blocks and adds a header containing routing information, determined by a destination processor, to each bit data block for conversion into plural cells, and sends those cells to the ATM switches 2 in parallel. The cells are transferred in parallel to the destination processor by the ATM switches 2 and reassembled into the original data block at the interface of the destination processor.
申请公布号 JPH06187311(A) 申请公布日期 1994.07.08
申请号 JP19930217205 申请日期 1993.09.01
申请人 HITACHI LTD 发明人 TAKAHASHI YASUHIRO;HOSHI TORU
分类号 G06F13/38;G06F15/16;G06F15/173;H04Q3/545 主分类号 G06F13/38
代理机构 代理人
主权项
地址