PROGRAMMABLE INTERCONNECT ARCHITECTURE

摘要

A programmable interconnect system includes a two-level hierarchical structure of programmable interconnect chips (120.1-120.6 and 130.1-130.2) on a circuit board (110). The first-level, or "local", interconnect chips are connected to user components (150.1-150.5). A plurality of second-level, or "global", interconnect chips interconnect the local interconnect chips so that every local chip is connected to every global chip. Such a system allows connecting any pin of any user component to any other pin of any user component by a conductive path passing through at most three interconnect chips. A large number of such paths are provided even in embodiments with a large number of interconnect chips.