发明名称 |
Gittercodierte Modulationsvorrichtung |
摘要 |
A 2/3 convolutional encoder includes a first adder 340 for outputting a first output bit 306 by a modulo-two sum of a present input bit 301 and a twice-delayed input bit 304 of an upper stage, a present input bit 302 and a once-delayed input bit 305 of a lower stage, among 3-bit output bits; a second adder 350 for outputting a second output bit 307 by a modulo-two sum of a once-delayed input bit 303 and a twice-delayed input bit 304 of the upper stage and a present input bit 302 of the lower stage; and a third adder 360 for outputting a third output bit 308 by a modulo-two sum of a present input bit 301 of the upper stage and a once-delayed input bit 305 of the lower stage. A trellis-coded modulation system includes such a convolutional coder (210), Fig. 3, (not shown) for receiving and encoding data (202); a mapper (220) for inputting the remaining uncoded bit (201) and the bits (205) coded by the coder and outputting digital valves of components (206), (207), for signal points of a constellation; a modulator (230) for modulating the bit signals output from the mapper; and a synchronization controller (240) for controlling the coder and mapper. An alternative encoder and mappers are described. <IMAGE>
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申请公布号 |
DE4344811(A1) |
申请公布日期 |
1994.07.07 |
申请号 |
DE19934344811 |
申请日期 |
1993.12.28 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD., SUWON |
发明人 |
PARK, HYUN-WOO, SUWON;GONG, JUN-JIN, SEONGNAM;LEE, TAK-HUN, KYUNGKI |
分类号 |
H04L25/08;H03M13/23;H03M13/25;H04L27/34;H04L27/36;(IPC1-7):H03M13/12;G11B20/18 |
主分类号 |
H04L25/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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