DATA INTEGRITY CHECK IN BUFFERED DATA TRANSMISSION

摘要

A process and device are disclosed for checking data provided with parity bits and read into a buffer memory by means of a parity checker (100). The device has a first counter (20) connected with some of the memory input lines (25) by exclusive OR gates (30a-d) and a second counter (80) connected to the memory output lines (55) which correspond to the memory input lines (25) by means of exclusive OR gates (70a-d) between the parity checker (100) and the memory (50). Both the first (20) and the second (80) counters generate continuous binary values. The process comprises the following steps: linking the read data with a value generated by the first counter (20) by an exclusive OR operation; writing the logically linked data into the memory (50); reading the logically linked data out of the memory (50); logically linking the read-out logically linked data to a value generated by the second counter (80) by an exclusive OR operation; and checking the read-out data for parity in the parity checker (100). The invention is useful in a buffer memory (50) between two asynchronously timed busses.