Parallel A/D converter having comparator threshold voltages defined by MOS transistor geometries

摘要

A comparator includes a P-channel MOS transistor connected at the source thereof to a power source and at the drain thereof to a comparator output and the drain of an N-channel MOS transistor. The source of the N-channel MOS transistor is connected to the ground. The gates of the P-channel MOS transistor and the N-channel MOS transistor are connected to a comparator input. The logic threshold voltage of the comparator is adjusted in accordance with a circuit parameter regarding the P-channel MOS transistor and the N-channel MOS transistor such as, a gate length, a gate width or a voltage of the power source. A result of comparison by the comparator between an analog input value inputted to the comparator input and the logic threshold voltage of the comparator is outputted to the comparator output. An analog to digital converter is constructed using the comparator. The analog to digital converter is reduced in size and allows high speed analog to digital conversion.