| 摘要 |
An arithmetic circuit for calculating and accumulating absolute values of a difference between a first and a second numerical value has a predetermined bit length and is represented by 2's complement notation and outputting an accumulation result as an operation result. The circuit comprises first inverting means for inverting the second numerical value to produce an inverted value; first adder means for producing a sum of the first numerical value and the inverted value and outputting the sum as a first addition result; second inverting means for inverting the first addition result to output an inverted addition result. Selecting means select either one of the inverted addition result and the first addition result on the basis of a sign of the first addition result and output the one result as a selected value. Correcting value generating means output a correcting value on the basis of a sign of the first addition result and second adder means produce a sum of the selected value, the correcting value and a delayed addition result and output the sum as a second addition result. First delaying means delay the second addition result by a predetermined delay to produce the delayed addition result while outputting the delayed addition result as the operation result.
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