发明名称 |
Method of testing redundant memory cells |
摘要 |
In a single chip semiconductor memory, having independent memory areas for normal memory cells and redundant memory cells, the redundant cells are tested in a parallel or multi-bit test mode simultaneously with the normal cells they replace, by enabling the redundant memory area in response to simultaneous detection of the state of the multi-bit test mode, the presence of a programmed redundant bit for a memory cell under test, and the operative selection of the normal memory matrix.
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申请公布号 |
US5327382(A) |
申请公布日期 |
1994.07.05 |
申请号 |
US19920942627 |
申请日期 |
1992.09.09 |
申请人 |
SENO, KATSUNORI;KNORPP, KURT |
发明人 |
SENO, KATSUNORI;KNORPP, KURT |
分类号 |
G01R31/28;G11C29/04;G11C29/24;(IPC1-7):G11C7/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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