发明名称 Clock control apparatus.
摘要 <p>A clock control apparatus having a basic period clock and a plurality of clocks with different phases from the basic period clock by t/N period, is used with an information processing unit. The apparatus comprising a clock signal generating portion for generating pulses of the basic period clock, a cycle counter for counting the number of pulses of the basic period clock received from the clock signal generating portion when a start command is received and for outputting a cycle counter clock stop signal when the number of pulses becomes a predetermined count value, a control portion for outputting a basic enable period signal for controlling the basic period clock and a delay enable period signal for controlling the t/N period clocks by a flag and the cycle counter clock stop signal, the flag being assignable before the start command is received, a basic period clock enabling portion for receiving pulses of the basic period clock and for outputting the pulses of the basic period clock for a period designated by the basic enable period signal, and a t/N delay period clock enabling portion for generating pulses of the t/N period clock and for outputting the pulses for a period designated by the delay enable period signal. &lt;IMAGE&gt;</p>
申请公布号 EP0603996(A2) 申请公布日期 1994.06.29
申请号 EP19930307162 申请日期 1993.09.10
申请人 FUJITSU LIMITED 发明人 KOMATSUDA, HIROSHI, C/O FUJITSU LIMITED
分类号 G06F1/04;G06F11/00;(IPC1-7):G06F1/06 主分类号 G06F1/04
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