发明名称 |
COMPUTER SYSTEM WITH INTERMEDIATE ADDRESS INTERRUPTION |
摘要 |
PURPOSE:To reduce the burdens of a CPU in a continuous reproducing processing such as a continuous sound reproducing processing in a computer system provided with a memory for a data buffer. CONSTITUTION:This system is a means for automatically shifting a point to a start address after transferring the data of the end address of a data area provided in the memory for the data buffer and performing continuous reproduction and interruption is generated when the point reaches to the end address and an intermediate address set between the start address and the end address. By updating a first half by receiving intermediate address interruption and updating a last half by receiving end address interruption, the continuous reproduction is enabled. |
申请公布号 |
JPH06180639(A) |
申请公布日期 |
1994.06.28 |
申请号 |
JP19920284982 |
申请日期 |
1992.10.01 |
申请人 |
HUDSON SOFT CO LTD;SEIKO EPSON CORP |
发明人 |
TOMITA MASAHIDE |
分类号 |
G06F3/16;G10L19/00;G11B7/00;G11B7/005 |
主分类号 |
G06F3/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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