| 摘要 |
A high-speed multiplier utilizing a layout architecture requiring very little area on a chip. The present invention employs a floor plan which exemplifies regularity and is approximately 33.3% more compact than conventional Wallace Trees. During a first phase of a first clock cycle, Booth coding takes place resulting in a first group of partial products. In a second phase of the first clock cycle, the first group of partial products are input into a first and a second carry-save adder. Results from the second carry-save adder are latched in a first and second register. Also during the second phase of the first clock cycle, a second group of partial products are Booth coded. In a first phase of a cycle 2, the second group of partial products are input into the first and second carry-save adders. Results from the second carry-save adder are latched into a third and fourth register. In a second phase of cycle 2, results from the first, second, third and fourth registers are input into a third and fourth carry-save adder. The outputs from the fourth carry-save adder are latched into a fifth and a sixth register. In a first phase of a cycle 3, results latched in the fifth and sixth registers are input into a CPA. The CPA then generates a final output for the multiplier.
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