| 摘要 |
PCT No. PCT/JP91/00406 Sec. 371 Date Jul. 29, 1992 Sec. 102(e) Date Jul. 29, 1992 PCT Filed Mar. 28, 1991 PCT Pub. No. WO91/15856 PCT Pub. Date Oct. 17, 1991.This invention, which relates to the output circuit of a sense amplifier that amplifies the signal read from the memory, maintains the output signal stably at a specified level in the presence of equalize pulse signals. Differential amplifiers (36a, 36b) amplify a pair of complementary signals read from the memory. The output terminals of these differential amplifiers (36a, 36b) are connected to each other by transfer gates (N1, P1) controlled by the equalize pulse signals (EQ, /EQ) and also connected to latch circuits (13, 14) via clocked inverter circuits (11, 12). The clocked inverter circuits (11, 12) are put in a high impedance state during the presence of the equalize pulse signals, so that the signals held in the latch circuits (13, 14) remain unchanged.
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