发明名称 FORMATION OF WIRING
摘要 PURPOSE:To satisfy both planarization of contact holes on a semiconductor substrate and subsequent planarization of an interlayer film while preventing microminiaturization of Al crystal particle in an Al alloy film formed on a barrier unetal layer and lowering electromigration resistance. CONSTITUTION:An Al alloy wiring material 4 is deposited by 8000Angstrom thick through high temperature bias sputtering at 450 deg.C on a silicon substrate 1 provided with a barrier metal layer 2 having a contact hole 3 thus filling the contact hole 3 and planarizing the surface. The Al alloy layer 4 is then etched back by RIE, for example, to 4000Angstrom thick which causes no trouble in planarization of interlayer film and a wiring pattern is baked through lithographic process followed by formation of a wiring 5 by RIE. This method allows filling of contact hole and planalization of interlayer film through high temperature sputtering of Al at such thickness as causing no trouble in planarization of interlayer film.
申请公布号 JPH06177127(A) 申请公布日期 1994.06.24
申请号 JP19910155763 申请日期 1991.05.30
申请人 SONY CORP 发明人 KOYAMA KAZUHIDE
分类号 H01L21/28;H01L21/3205;H01L21/3213;H01L21/768;H01L23/52;H01L23/522;(IPC1-7):H01L21/320;H01L21/90 主分类号 H01L21/28
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