| 摘要 |
PURPOSE:To reduce cost by reducing the hardware amount of a computing element and to suppress the deceleration of processing speed at the time of arithmetic with double accuracy as high as that of the computing element. CONSTITUTION:A selector 6 outputs the output of a computing element 4 or a clip value to a bus 3a. A temporary register 5 holds the output 6f the computing element 4, and a second selector 7 outputs the output of the register 5 or the clip value to a bus 3b. A control part 8 stores the low-order arithmetic result in the register 5 in the first cycle of arithmetic with the double accuracy as high as that of the computing element 4. When the high-order arithmetic result overflows in the second cycle, the control part 8 clips and outputs the arithmetic result and the output of the register 5 by using the selectors 6 and 7, and they are stored in a register group 1. On the other hand, when the high- order arithmetic result does not overflows in the second cycle, the control part 8 outputs the arithmetic result and the output of the register 5 by using the registers 6 and 7 as they are, and they are stored in the register group 1. |
