| 摘要 |
<p>PURPOSE:To reduce the potential of high voltage which is boosted in a chip to erase and write, to release a requirement for breakdown voltage of the junction of a EEPROM, and to easily increase integration. CONSTITUTION:At the time of erasing, negative high voltage of -15V is applied to a control gate CG of a selected FETMOS memory cell 3, while low voltage of +5 V is applied to a P type well 2. At the time of writing, high voltage of +18V is applied to the control gate CG of the selected FETMOS memory cell 3, while low voltage of -2V is applied to a P type well 2.</p> |
