发明名称 DECODER CIRCUIT AND SEMICONDUCTOR DEVICE
摘要 <p>PURPOSE:To obtain an inexpensive decoder circuit which has such a function that word lines or bit lines are made all selective or all non-selective in a test mode with simple circuit constitution without increasing a circuit scale of a whole decoder circuit, also is suitable for increasing integration. CONSTITUTION:This circuit is a decoder circuit 1 in a semiconductor memory. An output stage or a decoding stage of the decoder circuit 1 is connected to a first power supply 4 which supplies a high potential voltage and a second power supply 5 which can supply either of a reference potential voltage and a high potential voltage by a control signal.</p>
申请公布号 JPH06176599(A) 申请公布日期 1994.06.24
申请号 JP19920324284 申请日期 1992.12.03
申请人 FUJITSU LTD 发明人 KAWAMURA SHOICHI;KAWASHIMA HIROMI
分类号 G11C11/413;G11C11/407;G11C11/408;G11C16/06;G11C17/00;G11C29/00;G11C29/06;G11C29/12;(IPC1-7):G11C29/00 主分类号 G11C11/413
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