| 摘要 |
PURPOSE:To avoid malfunction even when the clocked inverter circuit is used for a latch circuit and a shift register or the like by surely switching the inverter operation of a couple of the inverter circuits even when a phase of a clock signal and an inverted clock signal differs from each other and the duty ratio is not complementary. CONSTITUTION:When clock signals phi and inverse of phi go to an H level simultaneously or to an L level, an inverter circuit 1 is set to a high impedance state to allow an inverter circuit 2 to make the inverter operation. Then an output of a NAND gate 12d of a pull-up control section 12 and an output of a NOR gate 13d of a pull-down control section 13 go respectively to H and L level and an output of a NOR gate 22d of a pull-up control section 22 and an output of a NAND gate 23d of a pull-down control section 23 go respectively to L and H level to output an inverse signal level at all times. Thus, the simultaneous inverter operation of the circuits 1, 2 is avoided to ensure the switching. |
