| 摘要 |
PURPOSE:To suppress a phase fluctuation of an output at a change of an input reference clock from 'interruption' into 'presence' and vice versa. CONSTITUTION:When an interruption detection circuit 16 detects 'interruption' of a reference clock signal RC, a clock signal MC obtained by applying 1/M frequency division to a standby clock signal BC outputted from a standby oscillator 18 at a 1/M frequency divider circuit 19 is phase-controlled by a clock signal NC obtained by applying 1/N frequency division to an output clock signal OC outputted from a voltage controlled oscillator 13 at a 1/N frequency divider circuit 14. On the other hand, when the reference clock signal RC is normal, a clock signal LC obtained by applying 1/L frequency division to the reference clock signal RC at a 1/L frequency divider circuit 17 is phase-controlled by a clock signal NC obtained by applying 1/N frequency division to an output clock signal OC outputted from the voltage controlled oscillator 13 at the 1/N frequency divider circuit 14. |
