| 摘要 |
PURPOSE:To prevent the deterioration of the capability of a processor even when one bit error is frequently generated by reading the counted value of a counter means in a prescribed cycle, and discriminating the abnormality of a storage device when it is more than a preliminarily decided reference value. CONSTITUTION:At first, at the time of data reading from a processor 11, when one bit error is detected at a main storage device 12, an ECC mechanism part 17 corrects it, and sets the value of the counter 18 as +1. And also, the upper limit value of the counter value is preliminarily decided, and when the number of times of one bit error correction is beyond the upper limit value, the counter value is not updated any more. On the other hand, a constant cycle reading means 14 of the processor 11 reads the counter value of the main storage device 12 in a certain cycle. And also, every hour or every day or the like is appropriately selected as the cycle. |
