| 摘要 |
<p>PURPOSE:To provide a processing circuit with a smaller circuit scale by eliminating the need for a delay circuit of the device rearranging picture data used for a conventional processing circuit. CONSTITUTION:The processing circuit is provided with a picture memory by one page, 1st and 2nd address memories 104, 105 recording m-sets of addresses, 1st and 2nd selectors 106, 107 selecting outputs of the 1st and 2nd address memories 104, 105, an output address generating section 112 receiving an output of the 1st selector 106 to control the picture memory, an input address generator 113 receiving an output of the 2nd selector 107 to control the picture memory, an output read address generator 108 and an input side read address generator 109 controlling the address memories 104, 105, and 3rd and 4th selectors 110, 111 selecting outputs of the output and input side read address generating sections 108, 109 to generate a control address of the picture memory.</p> |
