发明名称 NETWORK FOR ADJUSTMENT OF DATA SPEED OF VIRTUAL CIRCUIT BY ASYNCHRONOUS TIME- DIVISION MULTIPLEX TRANSMISSION
摘要 <p>PURPOSE: To avoid overloading an ATM circuit and to give minimum delay to a channel by controlling the emission of a cell by means of the generation of a signal whose frequency is equal to data speed or average data speed against the respective data speed of the operation channels with the output of buffer memories in the frequency. CONSTITUTION: R-pieces of input channels (ch) are inputted to a memory cell MC provided with an input memory interface 2 and r-pieces of buffer memories MC1 -MCr . An interface 4 receives information on the data speed of respective channels. Information on the input channel is inputted to a table 5. A control member 7 recognizes that channel data speed and the number of channels are compatible with the arrangement of a circuit network. When the conditions are not realized, an alarm block 8 is triggered and the programming of the interface 4 is corrected. Channel information of the table 5 is inputted to units 9 and 11 and the unit 9 gives a priority number to a table 12. The channel number of the highest priority selected in an automatic unit 16 from data is transmitted to an address selection circuit 21 and is transmitted to the memory cell MC in the form of a read command through a conductor 23.</p>
申请公布号 JPH06177906(A) 申请公布日期 1994.06.24
申请号 JP19930192230 申请日期 1993.08.03
申请人 PHILIPS ELECTRON NV 发明人 SUADO DAMIYAN
分类号 H04L7/00;H04J3/24;H04L12/56;(IPC1-7):H04L12/48 主分类号 H04L7/00
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