Integrated solid state circuit with internal signal propagation delay compensation

摘要

The integrated solid state circuit has a logic stage (1) with NAND gates (6a-6d) with inputs (I1, I2) and outputs (5a-5d). The circuit is controlled by output enable signals (OE1, OE2) and a synchronising clock signal (CLK). Built into the integrated circuit is a ring oscillator (7), with the output applied to the trigger input of a bidirectional counter (8). The delay period is indicated by the number of pulses counted and can be used in a synchronising clock correction circuit.