发明名称 DELAY PULSE GENERATOR
摘要 <p>PURPOSE:To provide a delay pulse generator which achieves a smaller size and a lower cost with a high accuracy by providing a delay time control means with a multi-phase clock generation means, a clock section means and a pulse generation starting means which counts a clock signal selected to output a pulse generation start signal to a pulse generation means based on the counts. CONSTITUTION:A high-frequency multi-phase clock generation section 12 outputs (m) type of high-frequency clocks f1, f2 and fm synchronous to a reference signal (a) from a transmission start reference signal generating section 11. Two clocks g1 and g2 are selected by clock selection sections 13a and 13b from among the (m) type of high-frequency clocks to be sent to counters 14a and 14b. After reset by the reference signal (a), the counters 14a and 14b start counting and a counter output is inverted when counts thereof coincide with a preset value. A counter 15 receives the output as counting start command signal and gets the output of the counter inverted immediately after the counts reach a preset value.</p>
申请公布号 JPH06169916(A) 申请公布日期 1994.06.21
申请号 JP19920349996 申请日期 1992.12.03
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SORINAKA YOSHINAO;WATANABE YOSHINOBU;NAKAMURA YASUHIRO
分类号 A61B8/00;G05B24/02;G06F1/06;G10K11/34;H03K5/135;(IPC1-7):A61B8/00 主分类号 A61B8/00
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