发明名称 |
Integration of high voltage lateral MOS devices in low voltage CMOS architecture using CMOS-compatible process steps |
摘要 |
Region forming steps or interconnect-forming steps through which low voltage CMOS devices are formed in a semiconductor wafer are also employed to simultaneously form one or more regions or layers at selected sites of a substrate where high voltage devices are to be formed. Such selective modification of an already existing mask set designed for low voltage CMOS topography allows additional doping of the substrate or provision of further overlay material to accommodate the effects of high voltage operation of selected areas of the water and thereby effectively performs precursor tailoring or modification of those portions of the wafer where a high voltage condition will be encountered.
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申请公布号 |
US5322804(A) |
申请公布日期 |
1994.06.21 |
申请号 |
US19920882070 |
申请日期 |
1992.05.12 |
申请人 |
HARRIS CORPORATION |
发明人 |
BEASOM, JAMES D. |
分类号 |
H01L21/8234;H01L21/8238;H01L27/088;H01L29/423;H01L29/78;(IPC1-7):H01L21/70 |
主分类号 |
H01L21/8234 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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