发明名称 |
Semiconductor memory device having multiple memory arrays and including redundancy circuit for repairing a faulty bit |
摘要 |
Column repairing circuits 7a, 7b for repairing a DRAM in which there are defective memory cells in two columns are disclosed. The connection state of switching elements or circuits 51-5n, 61-6n, 71-7 (n+1), 81-8 (n+1) is determined as illustrated by appropriately disconnecting fuses in fuse links provided respectively in circuits 7a, 7b. Accordingly, column selecting lines Y2a and Y (n+1) b in memory array blocks 891a, 891b are not activated. The two repairing circuits 7a, 7b are provided spaced apart from each other on a semiconductor substrate, so that excessive concentration of fuse elements and switching elements or circuits is prevented. |
申请公布号 |
US5323348(A) |
申请公布日期 |
1994.06.21 |
申请号 |
US19910767316 |
申请日期 |
1991.09.30 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
MORI, SHIGERU;MOROOKA, YOSHIKAZU;MIYAMOTO, HIROSHI;KINOSHITA, MITSUYA;SUWA, MAKOTO;KIKUDA, SHIGERU;YAMADA, MICHIHIRO |
分类号 |
G11C11/401;G11C11/409;G11C29/00;G11C29/04;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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