| 摘要 |
An MIS device which includes a source diffusion layer and a drain diffusion layer under the surface of a semiconductor substrate, and a plurality of gate insulation films on the surface of the semiconductor substrate. Further, a plurality of gate electrodes are formed on the plurality of gate insulation films in series with one another between the source diffusion layer and the drain diffusion layer. Moreover, inter-gate-electrode diffusion layers are formed under the surfaces of regions of the semiconductor substrate among the plurality of the gate electrodes. Insulating side walls are provided on both sides of each of the gate electrodes. Furthermore, conductive layers are provided, each for covering at least one of the inter-gate-electrode diffusion layers among the plurality of the gate electrodes and covering the insulating side walls provided on that one inter-gate-electrode diffusion layer, and filling a depression surrounded by the insulating side walls and that one inter-gate-electrode diffusion layers. An insulation layer covers the gate electrodes and the conductive layers, at least partly. A conductive wiring layer on the insulation layer is in contact with a part of the conductive layer, which is not covered by the insulation layer. The conductive layers at both sides of at least one of the gate electrodes are selectively interconnected on that gate electrode. Thus at least one of the inter-gate-electrode diffusion layers provided among the plurality of the gate electrodes, which are used in a memory cell, is covered by a conductive layer. As the result, the transconductance of an enhancement type transistor can be increased. An amplification factor and a switching speed of the enhancement type transistor can be improved. Consequently, a high-speed operation can stably be performed.
|
