| 摘要 |
A CMOS power-up reset circuit provides a power-up output signal, useful to external circuits, when an applied power supply voltage exceeds a first predetermined value, and includes a ratioed transistor divider to generate a voltage on a sensing node which is a portion of the power supply voltage during a power-up transient. The circuit regeneratively latches when the rising power supply voltage and the sensing node voltage differ by more than a second predetermined value, such as a P-channel threshold voltage. A feedback signal subsequently disables current flow through the power-up reset circuit to virtually eliminate static power dissipation, and the power-up output signal is generated. Circuit provisions are incorporated to prevent capacitive coupling from the rising power supply voltage, through the N-wells of the P-channel transistors, to critical internal circuit nodes. The first predetermined value of the applied power supply voltage at which the circuit provides a power-up output signal is configurable by adjusting the ratio of two P-channel transistors.
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