Method for observing program flow in a processor having internal cache memory.

摘要

This invention relates to a cache processor and a method for observing program flow in a cache processor. Program flow can be reconstructed utilising program instruction information from at least one status pin (VF or VFLS) of the processor and the target addresses of jump instructions which addresses are available from the bus pins of the processor during a special show cycle. The program instruction information comprises data indicating the type of instruction fetched during a previous cycle, the type of instruction being either a non-jump or a jump instruction. The program instruction information and the target addresses are stored in first (26) and second (28) parts of memory respectively. <IMAGE>