Binary multiplier.

摘要

A technique of binary multiplication comprises storing one operand and a partial product in latches of a CPU. The second operand is stored in a shift register which is added to the CPU. The data in the shift register is shifted from the least significant bit to the most significant bit, with a "0" being loaded into the least significant bit. As the bits in the first operand are designated in sequence, the value of the partial product is increased by the value in the shift register if the designated bit is a "1". After the sequencing has designated all the bits of the first operand, the partial product is taken to be the product of the multiplication.