发明名称 HIGH RESISTANCE LOAD TYPE SRAM INTEGRATED CIRCUIT
摘要 PURPOSE:To detect the decrement of a high resistance constituting a high resistance load type memory cell and a junction leakage defect without injuring a function as a memory integrated circuit. CONSTITUTION:High resistors HR1 and HR2 constituting the high resistance load type memory cell 10 are made switchable to a state connected to power source, a state connected to ground and a state connected to any of no power source and no ground. Then, bit lines B, B<-> are made separatable from precharging lines 3, 4, and the value of currents flow through the bit lines B, B<-> are made measurable individually by current detection type amplifiers 13, 14.
申请公布号 JPH06168593(A) 申请公布日期 1994.06.14
申请号 JP19920320880 申请日期 1992.11.30
申请人 KAWASAKI STEEL CORP 发明人 SHIBATA KEIJI
分类号 G11C11/413;G11C29/00;G11C29/04;H01L21/8244;H01L27/11 主分类号 G11C11/413
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