| 摘要 |
<p>PURPOSE:To reduce the number of rewrite operation times for a comparison value at the time of generating a complicated pulse signal and to reduce the burden of CPU by comparing the respective bits of a count value with the respective bits of an arbitrary comparison value. CONSTITUTION:Prior to the generation of a signal, a value equivalent to T3 is set in a first comparison value register 13 and it is set to be a first comparison value A. A value equivalent to T3+T4 is set in a second comparison value register 14 and it is set to be a second comparison value B. When a clear signal CLR is inputted in such a state, a counter 10 is reset, and the count value C is counted up whenever a basic clock CLK is inputted. When the count value C reaches the first comparison value A, a transition timing decision signal Tma indicating the rise of a main pulse is fetched. When the count value C reaches the second comparison value B, a transition timing decision signal Tmb indicating the fall of the main pulse is fetched. An arbitrary value is written into designation bit information Ba and Bb and an auxiliary pulse is outputted.</p> |
