| 摘要 |
PURPOSE:To obtain the pattern generating circuit varying a received pattern generating clock signal to a signal having an optional bit length by using a fixed length pattern signal as a trigger to control the pattern generating clock signal inputted to the pattern generating circuit. CONSTITUTION:A shift register 4 receives a pattern generating clock signal 12 and an input clock signal 11 having a period of a multiple of an integer and outputs a signal delaying the signal 12. A selector 5 receives the output of the register 4 and outputs a selected signal by switches 5A, 5B. A gate 6 receives the signals 11, 12, an inverting output 17 of the selector 5 and a fixed length pattern signal 22 and outputs a bit adjustment clock signal 18. A gate 7 receives the signal 12 and the inverted signal 18 and outputs a variable bit length generating clock signal 19. A frequency divider circuit 1 receives the signal 19 and outputs frequency division signals 20, 21 and a selector 3 receives the output of a switch 2 through which a preset signal is outputted. The selector 3 receives the signals 20, 21 to select the switch 2 and outputs the fixed length pattern signal 22. |
