发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <p>PURPOSE:To eliminate the redundancy of delay, to quicken the system operation and to expand the operating margin of the system by optimizing a delay circuit with respect to the system. CONSTITUTION:A source of a p-channel transistor (hereinafter called p-Tr)Qp of a CMOS inverter being a component of a delay circuit is connected to a point of a semiconductor inside voltage drop level Vint and a substrate is connected to a point of an external power supply level Vext. Then, the delay circuit is formed by combining an inverter having the p-TrQp connected in this way and an inverter having the p-TrQp whose source and substrate are both connected to the point of the external power supply level Vext.</p>
申请公布号 JPH06169240(A) 申请公布日期 1994.06.14
申请号 JP19920341418 申请日期 1992.11.27
申请人 NEC CORP 发明人 NAGANAMI TORU
分类号 H01L27/02;H03K5/00;H03K5/13;(IPC1-7):H03K5/13 主分类号 H01L27/02
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