Zero-consumption power-on reset circuit

摘要

A power-on reset circuit, which may be utilized with CMOS integrated circuits, includes first and second series-connected inverters, wherein the output of the second inverter provides a reset signal. A series of switches and a biasing line having two series-connected diodes are integrally arranged with the inverters. Capacitive coupling to ground and the supply voltage is employed to prevent any static current path between supply voltage rails. The circuit provides a short duration reset signal which follows the supply voltage and is insensitive both to rebound signals on the supply voltage rails and to internal and external noise.