| 摘要 |
According to the frequency multiplier of the present invention, an output clock signal of multiplied frequency is emitted from an exclusive NOR circuit which enters an input clock signal and a signal obtained by delaying the input clock signal via a first delay circuit. To the first delay circuit, second and third delay circuits are sucessively cascaded to delay the input clock signal. A circuit which comprises two flip-flops is supplied with the input clock signal and the output of the third delay circuit to emit a set signal when the rise in output of the third delayed circuit becomes faster than the fall of the input clock signal due to change in the delay time caused by the external conditions. Further, another circuit, which also comprises two flip-flops, is supplied with the input clock signal and the output of the second delay circuit, and emits a set signal when the rise in output of the second delay circuit becomes more delayed than the fall of the input clock signal due to the above change in the external conditions. These set signals can operate a blocking flip-flop circuit to block the output clock signal so that the fluctuation of the duty factor of the output clock signal, due to the change of the delay time of the first delay circuit, may be restricted within a predetermined range.
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