High speed timing generator

摘要

A high speed timing generator including a pattern generator circuit, a plurality local generator circuits associated with respective nodes of a device under test, and a plurality of distribution paths. The pattern generator circuit has a high speed pattern generator which generates a high speed address and a divider circuit which divides the high speed address into a plurality of lower speed address patterns at a lower frequency. Each local generator circuit has a plurality of signal generator circuits which operate at the lower frequency of the lower speed address patterns and provide lower frequency signals and a high speed formatter circuit which uses the lower frequency signals to provide a high frequency signal. The plurality of distribution paths provide the lower speed address patterns to the local generator circuit.