| 摘要 |
PURPOSE:To attain the high performance of a parallel multiplier constituted of 5-input/3-output unit adders by speeding up the unit adders. CONSTITUTION:By turning a first carry output COUT (*) of the unit adder into negative logic, and simultaneously, by generating the sum output of the critical path of the sum of XOR(1) and the inverse of XNOR-XOR(3), the replacement of an XOR gate to an XNOR gate and the equalization of the load capacity of each gate circuit can be realized, and delay time can be shortened while suppressing the increase of a circuit scale to the minimum. |
