发明名称 ASYNCHRONOUS UP/DOWN COUNTER
摘要 PURPOSE:To prevent the counter value from being disordered by locking the counter only in a disorder period of the counter value. CONSTITUTION:When an up/down switching signal 2 is varied, a detecting means 7 operates as mentioned below. Namely, a switching detection signal 10 becomes 09 when the held value of a D type flip-flop FF 8 is different from the value at a next clock edge; and T type FFs 510, 520, and 530 are locked, so that the detecting means does not operate even when an effective edge is applied to the clock input. Consequently, the counted value prevented from being disordered owing to a hazard (extremely narrow excessive pulse) which is generated at the time of count switching and exceeded. Then a clock signal 1 is applied to an FF 8 and a determination up/down switching signal 9 is outputted; and the switching detection signal 10 becomes 1 after an effective edge is switched by an exclusive OR circuit, thereby unlocking the T type FF 5. Then the counter counts in the direction which is switched to by the input of the signal 1. Thus, the counted value is prevented from being disordered.
申请公布号 JPH06164372(A) 申请公布日期 1994.06.10
申请号 JP19920310102 申请日期 1992.11.19
申请人 MITSUBISHI ELECTRIC CORP 发明人 SHIRAISHI TADAAKI;OGA TETSUAKI;ISHIDA HIROICHI;ISAKI TERUAKI;MASHIBA YUSUKE
分类号 H03K21/40;H03K23/00;H03K23/62;(IPC1-7):H03K23/00 主分类号 H03K21/40
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