发明名称 RESET SIGNAL GENERATING CIRCUIT
摘要 <p>PURPOSE:To obtain an optimum reset signal and to efficiently start the operation of a microcomputer, etc., by reset-resetting a certain time later since a sufficient operating voltage is obtained by starting constant-voltage operation. CONSTITUTION:When a source voltage VB rises sufficiently and a constant voltage output Vcc reaches a specific voltage at a point T2 of time, the constant voltage operation is started. Namely, the output voltage of a driving circuit 3 rises so as to make the bias of a transistor(TR) 1 shallow and becomes higher than the voltage of the constant output Vcc, so a TR 4 turns OFF and further a TR 5 turns OFF. The collector voltage of the TR 5, therefore, reaches Vcc, i.e., a level H and the output of a NAND gate 8 varies to a level L. Consequently, a TR 9 turns OFF to start charging a capacitor 10 through a resistance 11 and after a delay time determined by the time constant of the capacitor 10 and resistance 11 is elapsed, a reset signal *RES goes up to the level H at a point T3 of time, thereby resetting the resetting.</p>
申请公布号 JPH06164349(A) 申请公布日期 1994.06.10
申请号 JP19920318540 申请日期 1992.11.27
申请人 SANYO ELECTRIC CO LTD 发明人 MORIMOTO YOSHIHIDE
分类号 G06F1/24;G06F15/78;H03K17/22;H03K17/28;(IPC1-7):H03K17/22 主分类号 G06F1/24
代理机构 代理人
主权项
地址